1. Field of the Invention
The present invention relates to processing of digital signal trains formed by a sequence of binary data which occupy equal time intervals and more particularly to relocking of one or a number of binary signal trains having identical or submultiple data flow rates on a synchronous local clock signal so as to permit recovery by sampling of the exact values of the data contained in the digital signal train or trains. This operation, which is necessary for good reception of a binary data signal train, must also be performed in data-processing devices for receiving binary data at identical flow rates via different channels from separate sources having no known phase relationship.
2 Description of the Prior Art
Two categories of devices are already known for relocking a data signal train with respect to a synchronous clock signal. The devices of the first category such as those described in French patent Application No. FR-A-2,567,696 produce a set of versions of the binary data train with different time-delays uniformly distributed over the duration of a clock signal period, sample the entire set of versions by means of the clock signal and select the version having the best framing with respect to the clock signal as being the version in which sampling produces the same results as those of the other two more and less delayed versions which are located nearer to it on each side and possibly also of other more and less delayed versions which are located at a greater distance on each side. The devices of the second category such as those described in French patent Application No. FR-A-2,567,697 produce a reference version of the data train located between two other versions which are more and less delayed with respect to the clock signal. The three versions remain within a time-delay range which extends over one period of the clock signal and displace all three versions relatively to the clock signal in such a manner as to ensure that sampling of the three versions by the clock signal produces the same results. This relative displacement preferably takes place by imposing an adjustable time-delay on the data train from which the three delayed versions are derived, thus permitting optimum framing of the reference version with respect to the clock signal.
These two categories of relocking devices utilize a minimum of three versions of each data signal train to be relocked, these three versions being differently delayed with respect to each other, thus contributing to the complexity of these devices which rapidly increases with the number of data trains to be processed.